SoC

교육내용

SystemVerilog for Assertion

교육목표

SystemVerilog Assertion for digital design and verification

교육대상

Digital design & Verification engineer (prerequisite skill : Verilog/ SystemVerilog)

교육과정

Day 1

    - System Verilog Assertion for Simulation, Labs

Day 2

    - System Verilog Assertion for Formal, Labs